PROJEKTI
   

Project
Acronym: ROBUSPIC 
Name: ROBUst mixed signal design methodologies for Smart Power ICs - ROBUSPIC 
[PROJECT URL | CORDIS URL]
Project status: From: 2003-12-01 To: 2007-03-31 (Completed)
Contract number: 507653 
Action line: IST-2002-2.3.1.1 Pushing the limits of CMOS, preparing for post-CMOS 
Type (Programme): FP6 
Instrument: STREP 
Project cost: -
Project funding: -
Project coordinator
Organisation Name: AMI Semiconductor Belgium 
Organisation adress: Westerring 15, 9700 Oudenaarde, Belgium 
Organisation country: Belgija 
Contact person name: LAES, Edgard 
Contact person email:  
Croatian partner
Organisation name: Fakultet elektrotehnike i računarstva 
Organisation address: Unska 3, 10000 Zagreb 
Contact person name: BARIĆ, Adrijan
Contact person tel:
+385 1 6129 630  Contact person fax:  
Contact person e-mail: Email 
Partners
Organisation nameCountry
AMI SEMICONDUCTOR BELGIUM Belgija 
ROBERT BOSCH GMBH Njemačka 
CADENCE DESIGN SYSTEMS SAS Francuska 
CAMBRIDGE SEMICONDUCTOR LTD. Velika Britanija 
KATHOLIEKE UNIVERSITEIT LEUVEN Belgija 
ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE Švicarska 
IMEC - INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM VZW Belgija 
UNIVERSITY OF CAMBRIDGE Velika Britanija 
UNIVERSITY OF ZAGREB Hrvatska 
Short description of project
Smart power circuits and technologies contribute in a unique way to the realization of the system-on-chip concept by combining digital logic with analogue signal processing and power and high voltage switching. The main objective of this project is to enable a robust design of smart power circuits leading to a first-time-right design with built-in reliability and thus avoiding very costly over-dimensioning. To achieve this ambitious goal, compact models will be built that accurately describe power device operation including extensions to verify safe-operating area conditions. The devices to be modelled include the lateral DMOS, vertical DMOS and LIGBT fabricated in bulk silicon and power devices realized in advanced SOI technology. Model extensions are planned for device ageing due to hot-carrier injection, statistics due process variations, device matching and layout effects such as large area closed-cell matrices. An important feature will be an accurate description of the internal device temperature plus a coupling to package thermal models and EMC modelling. The final goal is to achieve a system level design flow for smart-power SoC using complex transistor level simulations or generated black-box models. Full smart power circuits will be simulated with the new design flow and models will be assessed and calibrated against experimental measurements. The gain in performance and robustness will be quantified. The project therefore aims at providing the EC "power" industrial community with new, highly robust tools to design and characterize smart power devices and circuits. This will strengthen and significantly advance ECs position as a fast growing, world supplier of smart power technologies. Design and fabrication of highly reliable and efficient Smart Power circuits is one of the most important strategic ways to reduce drastically energy losses in power systems by ensuring optimal energy conversion at all times. 
Short description of the task performed by Croatian partner
The task of the University of Zagreb is to investigate the role of the conducted EMC (electromagnetic compatibility )simulations in the IC design flow. The EMC simulations emphasize the importance of accurate parasitics extraction. The on-chip parasitics, both the circuit and power/ground line parasitics, have to be accurately determined as well as the influence of packaging, signal traces on the PCB and SMD components mounted on the PCB. Various netlisting strategies are demonstrated. The circuit simulations are performed within the Cadence design environment. The parasitics extraction of the power supply network is performed by Cadence Assura or 3D EM Ansoft tools HFSS or Q3D, and the results have been compared. The procedures for the extraction of on-chip parasitics, packaging and PCB parasitics by using 3D EM simulations are presented. Several EMC models are described. Also, the usage of the artificial neural network for EMI current source modelling is shown. An add-on tool for the simulation of EMC standards in the Cadence environment is developed. The procedure for optimization of integrated circuits (ICs) with respect to electromagnetic compatibility (EMC) is presented. The circuits are optimized by combining the global and local optimization approaches with the cost functions calculated by circuit simulations. The EMC test chips are designed and extensively measured and simulated. The EMC simulations of the EMC test chips are compared with measurements and found to be in very good agreement. The accuracy of the simulations is within the project targets and all the task requirements are fulfilled. 


   

Design by: M. Mačinković

(C)opyright by Sveučilište u Zagrebu,